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1 for more information www.linear.com/ltm8046 v in (v) 0 maximum output current (ma) 700 600 400 200 500 300 100 10 20 8046 ta01b 30 5 15 25 typical a pplica t ion fea t ures descrip t ion 3.1v in to 31v in , 2kvac isolated dc/dc module converter the lt m ? 8046 is an isolated flyback dc/dc module ? (micromodule) converter. the ltm8046 has an isolation rating of 2 kvac. included in the package are the switching controller, power switches, transformer, and all support components. operating over an input voltage range of 3.1v to 31 v, the ltm8046 supports an output voltage range of 1.8 v to 12 v, set by one resistor. only output, input, and bias capacitors are needed to finish the design. an optional capacitor can be used to set the soft-start period. the ltm8046 is packaged in a 9mm 15mm 4.92mm over-molded ball grid array ( bga) package suitable for automated assembly by standard surface mount equip - ment. the ltm8046 is available with snpb ( bga) or rohs compliant terminal finish. l, lt , lt c , lt m , linear technology, the linear logo and module are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. a pplica t ions n 2 kvac isolated module converter ( tested to 3 kvdc) n ul 60950 recognized ? , file e464570 n wide input voltage range: 3.1v to 31v n 5v at 550ma from 24v in n 1.8 v to 12v output voltage n current mode control n programmable soft-start n user configurable undervoltage lockout n snpb or rohs compliant finish n 9mm 15mm 4.92mm bga package n industrial sensors n industrial switches n ground loop mitigation maximum output current vs v in 2kv isolated low noise module regulator 2kvac isolation ltm8046 8046 ta01a v in 4.3v to 26v v out 5v 100f 1f 1f 8.45k v out v in run fb ss bias gnd v out ? isolation barrier ltm8046 8046fb
2 for more information www.linear.com/ltm8046 p in c on f igura t ion a bsolu t e maxi m u m r a t ings v in , run ................................................................... 32 v fb , ss ......................................................................... 5v v out relative to v out C .............................................. 16 v v in + 2v out ( note 5) ................................................. 36 v bias ................................................................ v in + 0.1 v gnd to v out C isolation ( note 2) ........................... 2 kvac max imum internal temperature ( note 3) .............. 125 c pea k solder reflow body temperature ................. 245 c (note 1) l k j h g f e d c b a top view 1 2 3 4 5 6 7 bank 4 v out bank 3 v out ? bank 2 gnd run fb bias ss bank 1 v in bga package 51-lead (15mm 9mm 4.92mm) t jmax = 125c, ja = 21.9c/w, jcbottom = 7.9c/w, jctop = 17.9c/w, jb = 8.4c/w weight = 1.5g, values determined per jedec 51-9, 51-12 o r d er i n f or m a t ion part number pad or ball finish part marking* package type msl rating temperature range (see note 3) device finish code ltm8046ey#pbf sac305 (rohs) ltm8046y e1 bga 3 C40c to 125c ltm8046iy#pbf sac305 (rohs) ltm8046y e1 bga 3 C40c to 125c ltm8046iy snpb (63/37) ltm8046y e0 bga 3 C40c to 125c ltm8046 mpy #pbf sac305 (rohs) ltm8046y e1 bga 3 C55c to 125c ltm8046 mpy snpb (63/37) ltm8046y e0 bga 3 C55c to 125c consult marketing for parts specified with wider operating temperature ranges. *device temperature grade is indicated by a label on the shipping container. pad or ball finish code is per ipc/jedec j-std-609. ? pb-free and non-pb-free part markings: www.linear.com/leadfree ? recommended lga and bga pcb assembly and manufacturing procedures: www.linear.com/umodule/pcbassembly ? lga and bga package and tray drawings: www.linear.com/packaging ltm8046 8046fb
3 for more information www.linear.com/ltm8046 e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltm8046 isolation is tested at 3kvdc for one second. note 3: the ltm8046e is guaranteed to meet performance specifications from 0c to 125c. specifications over the C40c to 125c internal temperature range are assured by design, characterization and correlation with statistical process controls. ltm8046i is guaranteed to meet specifications over the full C40c to 125c internal operating temperature range. the ltm8046mp is guaranteed to meet specifications over the full C55c to 125c internal operating temperature range. note that the maximum internal temperature is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. the l denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at t a = 25c, run = 12v (note 3). parameter conditions min typ max units minimum input dc voltage bias = v in , vrun = 2v bias open, vrun = 2v l l 3.1 4.3 v v v out dc voltage r fb = 14.7k r fb = 8.45k r fb = 3.83k l 4.75 2.5 5 12 5.25 v v v v in quiescent current v run = 0v 1 a v out line regulation 6v v in 31v, i out = 0.15a, vrun = 2v 1 % v out load regulation 0.05a i out 0.4a, vrun = 2v 1.5 % v out ripple (rms) i out = 0.1a, bw = 1mhz 20 mv isolation test voltage (note 2) 3000 vdc input short circuit current v out shorted 30 ma run pin input threshold vrun pin rising 1.18 1.24 1.30 v run pin current v run = 1v v run = 1.3v 2.5 0.1 a a ss threshold 0.7 v ss sourcing current ss = 0v C8 a bias current v in = 12v, bias = 5v, i out = 100ma 10 ma minimum bias voltage (note 4) i out = 100ma 3.1 v note 4: this is the bias pin voltage at which the internal circuitry is powered through the bias pin and not the integrated regulator. see bias pin considerations for details. note 5: v in + 2v out is defined as the sum of the voltage between (v in C gnd) added to twice the voltage between (v out C v out C ). ltm8046 8046fb
4 for more information www.linear.com/ltm8046 typical p er f or m ance c harac t eris t ics 5v out efficiency vs output current 8v out efficiency vs output current 12v out efficiency vs output current 1.8v out efficiency vs output current 2.5v out efficiency vs output current 3.3v out efficiency vs output current 1.8v out input current vs output current 2.5v out input current vs output current 3.3v out input current vs output current output current (ma) 0 efficiency (%) 75 70 65 60 45 50 55 600 8046 g01 800 200 400 12v in 5v in 24v in bias = 3.3v output current (ma) 0 efficiency (%) 80 75 70 65 60 50 55 8046 g04 600 200 400 12v in 5v in 24v in bias = 3.3v output current (ma) 0 efficiency (%) 75 70 65 60 50 55 600 8046 g02 700 200 400 500 100 300 12v in 5v in 24v in bias = 3.3v output current (ma) 0 efficiency (%) 75 70 65 60 50 55 600 8046 g03 700 200 400 500 100 300 12v in 5v in 24v in bias = 3.3v 80 60 70 50 40 65 75 55 45 output current (ma) 0 efficiency (%) 50 150 8046 g06 250 100 200 12v in 5v in bias = 3.3v output current (ma) 0 input current (ma) 250 100 50 0 150 200 200 600 8046 g07 800 400 bias = 3.3v 12v in 5v in 24v in output current (ma) input current (ma) 250 100 0 150 200 50 8046 g08 12v in 24v in 5v in bias = 3.3v 0 200 800 400 600 output current (ma) 0 efficiency (%) 80 75 60 55 65 70 50 200 8046 g05 500 400 300 100 12v in 5v in 20v in bias = 3.3v output current (ma) input current (ma) 300 250 0 150 200 100 50 8046 g09 12v in 5v in 24v in 0 200 600 400 400 bias = 3.3v ltm8046 8046fb
5 for more information www.linear.com/ltm8046 typical p er f or m ance c harac t eris t ics 5v out input current vs output current 8v out input current vs output current 12v out input current vs output current 1.8v out bias current vs output current 2.5v out bias current vs output current 3.3v out bias current vs output current 8v out bias current vs output current 12v out bias current vs output current 5v out bias current vs output current 0 800 400 200 output current (ma) input current (ma) 350 300 50 100 0 150 200 250 8046 g10 12v in 5v in 24v in bias = 3.3v output current (ma) input current (ma) 400 350 300 100 200 0 150 250 50 8046 g11 bias = 3.3v 0 200 500 400 300 100 5v in 12v in 20v in output current (ma) input current (ma) 400 250 350 0 150 300 200 100 50 8046 12 bias = 3.3v 0 100 250 200 150 50 5v in 12v in output current (ma) bias current (ma) 14 12 10 6 4 2 0 8 8046 g14 0 200 800 400 600 5v in 12v in 24v in bias = 3.3v output current (ma) bias current (ma) 8 12 0 10 14 4 6 2 8046 g16 0 600 400 200 5v in 12v in bias = 3.3v 24v in output current (ma) bias current (ma) 16 15 11 13 6 12 14 9 10 8 7 8046 g17 0 100 500 400 300 200 12v in bias = 3.3v 5v in 20v in output current (ma) bias current (ma) 16 15 14 10 12 6 11 13 8 9 7 8046 g18 0 250 150 200 100 50 bias = 3.3v 5v in 12v in output current (ma) bias currebt (ma) 11 10 6 8 4 7 9 5 8046 g13 0 800 600 400 200 5v in 12v in 24v in bias = 3.3v output current (ma) bias current (ma) 13 12 11 7 9 4 6 5 8 10 8046 g15 0 700 400 600500 300200100 24v in 12v in 5v in bias = 3.3v ltm8046 8046fb
6 for more information www.linear.com/ltm8046 typical p er f or m ance c harac t eris t ics maximum output current vs v in maximum output current vs v in minimum load vs v in minimum load vs v in 12v out minimum load vs v in input current vs v in output shorted temperature rise vs output current 3.3v out temperature rise vs output current 2.5v out output current (ma) temperature rise (c) 20 15 0 10 5 8046 g26 0 800 600 200 400 3.3v in 5v in 12v in 24v in v in (v) maximum output current (ma) 800 700 600 400 500 200 300 8046 g19 0 10 30 20 1.8v out 2.5v out 3.3v out bias = 3.3v v in (v) maximum output current (ma) 600 500 400 200 300 0 100 8046 g20 0 272421 3 6 9 12 15 18 5v out 8v out 12v out bias = 3.3v v in (v) minimum load (ma) 25 20 15 0 10 5 8046 g23 0 12 8 4 bias = 3.3v v in (v) input current (ma) 120 100 80 0 60 40 20 8046 g24 0 40 30 10 20 bias = 3.3v output current (ma) temperature rise (c) 20 15 0 10 5 8046 g25 0 800 600 200 400 3.3v in 5v in 12v in 24v in v in (v) minimum load (ma) 7 6 5 3 4 0 2 1 8046 g22 0 30 20 10 5v out bias = 3.3v 8v out minimum load (ma) v in (v) 35 30 25 15 20 0 10 5 8046 g21 0 32 24 8 16 1.8v out 2.5v out 3.3v out bias = 3.3v ltm8046 8046fb
7 for more information www.linear.com/ltm8046 typical p er f or m ance c harac t eris t ics temperature rise vs output current 8v out temperature rise vs output current 12v out output ripple step input start-up waveform temperature rise vs output current 5v out output current (ma) temperature rise (c) 20 15 0 10 5 8046 g27 0 700 500 600 100 200 300 400 3.3v in 5v in 12v in 24v in output current (ma) temperature rise (c) 20 0 15 5 10 8046 g29 0 300 100 200 3.3v in 5v in 12v in output current (ma) temperature rise (c) 15 0 10 5 8046 g28 0 100 200 300 400 3.3v in 5v in 12v in 24v in , 5v out 570ma load dc1559a demo board unmodified 150mhz bw 50mv/ div 8046 g30 2s/div 24v in , 5v out 20 resistive load 1v/ div 8046 g31 200s/div c ss = 0.1f c ss = 0.033f no c ss ltm8046 8046fb
8 for more information www.linear.com/ltm8046 p in func t ions v in (bank 1): v in supplies current to the ltm8046s internal regulator and to the integrated power switch. these pins must be locally bypassed with an external, low esr capacitor. gnd (bank 2): this is the primary side local ground of the ltm8046 primary. in most applications, the bulk of the heat flow out of the ltm8046 is through the gnd and v out C pads, so the printed circuit design has a large impact on the thermal performance of the part. see the pcb layout and thermal considerations sections for more details. v out C (bank 3): v out C is the return for v out . v out and v out C comprise the isolated output of the ltm8046. in most applications, the bulk of the heat flow out of the ltm8046 is through the gnd and v out C pads, so the printed circuit design has a large impact on the thermal performance of the part. see the pcb layout and thermal considerations sections for more details. apply an external capacitor between v out and v out C . v out ( bank 4): v out and v out C comprise the isolated output of the ltm8046 flyback stage. apply an external capacitor between v out and v out C . do not allow v out C to exceed v out . run ( pin l3): a resistive divider connected to v in and this pin programs the minimum voltage at which the ltm8046 will operate. below 1.24 v, the ltm8046 does not deliver power to the secondary. above 1.24 v, power will be de - livered to the secondary and 8 a will be fed into the ss pin. when run is less than 1.24 v, the pin draws 2.5a, allowing for a programmable hysteresis. do not allow a negative voltage (relative to gnd) on this pin. bias ( pin l4): this pin supplies the power necessary to operate the ltm8046. it must be locally bypassed with a low esr capacitor of at least 1 f. do not allow this pin voltage to rise above v in . ss ( pin l5): place a soft-start capacitor here to limit inrush current and the output voltage ramp rate. do not allow a negative voltage (relative to gnd) on this pin. fb (pin l6): apply a resistor from this pin to gnd to set the output voltage, using the recommended value given in table 1. if table 1 does not list the desired v out value, the equation r fb = 31.6 v out C0.84 ( ) k ? may be used to approximate the value. to the seasoned designer, this exponential equation may seem unusual. the equation is exponential due to non-linear current sources that are used to temperature compensate the output regulation. ltm8046 8046fb
9 for more information www.linear.com/ltm8046 b lock diagra m v in run fb *do not allow bias voltage to exceed v in gnd 0.1f 1f v out current mode controller v out ? ss bias* 8046 bd ? ? o pera t ion the ltm8046 is a stand-alone isolated flyback switching dc/dc module converter that can deliver over 700 ma of output current. this module provides a regulated output voltage programmable via one external resistor from 1.8v to 12 v. the input voltage range of the ltm8046 is 3.1v to 31 v. given that the ltm8046 is a flyback converter, the output current depends upon the input and output voltages, so make sure that the input voltage is high enough to support the desired output voltage and load current. the typical performance characteristics section gives several graphs of the maximum load versus v in for several output voltages. a simplified block diagram is given. the ltm8046 contains a current mode controller, power switching element, power transformer, power schottky diode, a modest amount of input and output capacitance. the ltm8046 has a galvanic primary to secondary isola - tion rating of 2 kvac. this is verified by applying 3kvdc between the primary to secondary for 1 second. note that the 2 kvac isolation is verified by a 3 kvdc test. this is because the 2 kvac waveform has a peak voltage 1.414 times higher than 2 kv, or 2.83 kvdc. for the ltm8046, at least 3kvdc is applied. for further details please refer to the isolation and working voltage section. an internal regulator provides power to the control cir - cuitry. the bias regulator normally draws power from the v in pin, but if the bias pin is connected to an external voltage higher than 3.1 v, bias power will be drawn from the external source, improving efficiency. v bias must not exceed v in . the run pin is used to turn on or off the ltm8046, disconnecting the output and reducing the input current to 1a or less. the ltm8046 is a variable frequency device. for a fixed input and output voltage, the frequency decreases as the load increases. for light loads, the current through the internal transformer may be discontinuous, so that frequency may appear to decrease. note that a minimum load is required to keep the output voltage in regulation. refer to the typical performance characteristics section. ltm8046 8046fb
10 for more information www.linear.com/ltm8046 a pplica t ions i n f or m a t ion for most applications, the design process is straight- forward, summarized as follows: 1. look at table 1 and find the row that has the desired input range and output voltage. 2. apply the recommended c in , c out and r fb . 3. connect bias as indicated, or tie to an external source up to 15v or v in , whichever is less. while these component combinations have been tested for proper operation, it is incumbent upon the user to verify proper operation over the intended systems line, load and environmental conditions. bear in mind that the maximum output current may be limited by junction temperature, the relationship between the input and output voltage magnitude and polarity and other factors. please refer to the graphs in the typical performance characteristics section for guidance. capacitor selection considerations the c in and c out capacitor values in table 1 are the minimum recommended values for the associated oper- ating conditions . applying capacitor values below those indicated in table 1 is not recommended, and may result in undesirable operation. using larger values is generally acceptable, and can yield improved dynamic response, if it is necessary. again, it is incumbent upon the user to verify proper operation over the intended system s line, load and environmental conditions. ceramic capacitors are small, robust and have very low esr. however, not all ceramic capacitors are suitable. x5r and x7r types are stable over temperature and ap - plied voltage and give dependable ser vice. other types, including y5v and z5u have very large temperature and voltage coefficients of capacitance. in an application cir - cuit they may have only a small fraction of their nominal capacitance resulting in much higher output voltage ripple than expected. a final precaution regarding ceramic capacitors concerns the maximum input voltage rating of the ltm8046. a ceramic input capacitor combined with trace or cable inductance forms a high-q ( underdamped) tank circuit. if the ltm8046 circuit is plugged into a live supply, the input voltage can ring to much higher than its nominal value, possibly exceeding the devices rating. this situation is easily avoided; see the hot-plugging safely section. table 1. recommended components and configuration (t a = 25c) v in v out c in c out r fb 3.2v to 32v 1.8v 1f, 50v, 0805 x5r 2 100f, 6.3v, 1206 x5r 18.7k 3.2v to 31v 2.5v 1f, 50v, 0805 x5r 2 100f, 6.3v, 1206 x5r 14.7k 3.2v to 29v 3.3v 1f, 50v, 0805 x5r 100f, 6.3v, 1206 x5r 11.8k 3.2v to 26v 5v 1f, 25v, 0603 x5r 100f, 6.3v, 1206 x5r 8.45k 3.2v to 20v 8v 1f, 25v, 0603 x5r 47f, 10v, 1206 x5r 5.49k 3.2v to 12v 12v 1f, 25v, 0603 x5r 2 10f, 16v, 1210 x5r 3.83k 3.2v to 25v 2.5v 1f, 25v, 0603 x5r 2 100f, 6.3v, 1206 x5r 14.7k 3.2v to 25v 3.3v 1f, 25v, 0603 x5r 100f, 6.3v, 1206 x5r 11.8k cbias = 1f 10v 0402 x5r bias = 3.3v for v in 3.3v, v in for v in < 3.3v. if bias = v in , the minimum input voltage is 4.3v. ltm8046 8046fb
11 for more information www.linear.com/ltm8046 a pplica t ions i n f or m a t ion bias pin considerations the bias pin is the output of an internal linear regulator that powers the ltm8046s internal circuitry. it is set to 3v and must be decoupled with a low esr capacitor of at least 1 f. the ltm8046 will run properly without apply - ing a voltage to this pin, but will operate more efficiently and dissipate less power if a voltage greater than 3.1 v is applied. at low v in , the ltm8046 will be able to deliver more output current if bias is 3.1 v or greater. up to 31v may be applied to this pin, but a high bias voltage will cause excessive power dissipation in the internal circuitry. for applications with an input voltage less than 15 v, the bias pin is typically connected directly to the v in pin. for input voltages greater than 15 v, it is preferred to leave the bias pin separate from the v in pin, either powered from a separate voltage source or left running from the internal regulator. this has the added advantage of keeping the physical size of the bias capacitor small. do not allow bias to rise above v in . soft-start for many applications, it is necessary to minimize the inrush current at start-up. the built-in soft-start circuit significantly reduces the start-up current spike and out - put voltage overshoot by applying a capacitor from ss to gnd. when the ltm8046 is enabled, whether from v in reaching a sufficiently high voltage or run being pulled high, the ltm8046 will source approximately 8 a out of the ss pin. as this current gradually charges the capaci - tor from ss to gnd, the ltm8046 will correspondingly increase the power delivered to the output, allowing for a graceful turn-on ramp. isolation working voltage and safety the ltm8046 isolation is 100% hi-pot tested by tying all of the primary pins together, all of the secondary pins together and subjecting the two resultant circuits to a differential of 3 kvdc for one second. this establishes the isolation voltage rating of the ltm8046 component. the isolation rating of the ltm8046 is not the same as the working or operational voltage that the application will experience. this is subject to the applications power source, operating conditions, the industry where the end product is used and other factors that dictate design requirements such as the gap between copper planes, traces and component pins on the printed circuit board, as well as the type of connector that may be used. to maximize the allowable working voltage, the ltm8046 has three rows of solder balls removed to facilitate the printed circuit board design. the ball to ball pitch is 1.27mm, and the typical ball diameter is 0.78 mm. accounting for the missing row and the ball diameter, the printed circuit board may be designed for a metal-to-metal separation of up to 4.3 mm. this may have to be reduced somewhat to allow for tolerances in solder mask or other printed circuit board design rules. to reiterate, the manufacturers isolation voltage rating and the required operational voltage are often different numbers. in the case of the ltm8046, the isolation voltage rating is established by 100% hi-pot testing. the working or operational voltage is a function of the end product and its system level specifications. the actual required operational voltage is often smaller than the manufacturer s isolation rating. for those situations where information about the spacing of ltm8046 internal circuitry is required, the minimum metal to metal separation of the primary and secondary is 1.9mm. the ltm8046 is a ul recognized com p onent under ul 60950-1, file number e 464570. the ul 60950-1 insula - tion categor y of the ltm8046 transformer is functional . considering ul 60950-1 t able 2 n and the gap distances stated above , 4.3 mm external and 1.9 mm internal, the ltm8046 may be operated with up to 400 v working voltage in a pollution degree 2 environment. the actual working voltage, insulation category, pollution degree and other critical parameters for the specific end application depend upon the actual environmental, application and safety compliance requirements. it is therefore up to the user to perform a safety and compliance review to ensure that the ltm8046 is suitable for the intended application. ltm8046 8046fb
12 for more information www.linear.com/ltm8046 a pplica t ions i n f or m a t ion figure 1 for a suggested layout. ensure that the grounding and heat sinking are acceptable. a few rules to keep in mind are: 1. place the r adj resistor as close as possible to its re- spective pin. 2. place the c in capacitor as close as possible to the v in and gnd connections of the ltm8046. 3. place the c out capacitor as close as possible to v out and v out C . 4. place the c in and c out capacitors such that their ground current flow directly adjacent or underneath the ltm8046. 5. connect all of the gnd connections to as large a copper pour or plane area as possible on the top layer. avoid breaking the ground connection between the external components and the ltm8046. 6. use vias to connect the gnd copper area to the boards internal ground planes. liberally distribute these gnd vias to provide both a good ground connection and thermal path to the internal planes of the printed circuit board. pay attention to the location and density of the thermal vias in figure 1. the ltm8046 can benefit from the heat sinking afforded by vias that connect to internal figure 1. layout showing suggested external components, planes and thermal vias 8046 f01 gnd gnd v in thermal/interconnect vias v out ? v out run fb bias ss v out to v out C reverse voltage the ltm8046 cannot tolerate a reverse voltage from v out to v out C during operation. if v out C raises above v out dur- ing operation, the ltm8046 may be damaged. to protect against this condition, a low forward drop power schottky diode has been integrated into the ltm8046, anti-parallel to v out /v out C . this can protect the output against many reverse voltage faults. reverse voltage faults can be both steady state and transient. an example of a steady state voltage reversal is accidentally misconnecting a powered ltm8046 to a negative voltage source. an example of transient voltage reversals is a momentary connection to a negative voltage. it is also possible to achieve a v out reversal if the load is short-circuited through a long cable. the inductance of the long cable forms an lc tank circuit with the v out capacitance, which drives v out negative. avoid these conditions. minimum load the ltm8046 requires a minimum load in order to main - tain regulation. if less than the minimum load is applied, the output voltage may rise beyond the intended value uncontrollably, possibly damaging the ltm8046 or the application system. avoid this situation . the typical performance characteristics section provides graphs of the minimum required load for several input and output conditions at room temperature. the ltm8046 is designed to skip switching cycles, if necessary, to maintain regulation. while cycle skipping, the output ripple may be higher than when the ltm8046 is not skipping cycles. the user must validate the perfor - mance of the ltm8046 application over the appropriate temperature, line, load and other operating conditions. pcb layout most of the headaches associated with pcb layout have been alleviated or even eliminated by the high level of integration of the ltm8046. the ltm8046 is neverthe - less a switching power supply, and care must be taken to minimize electrical noise to ensure proper operation. even with the high level of integration, you may fail to achieve specified operation with a haphazard or poor layout. see ltm8046 8046fb
13 for more information www.linear.com/ltm8046 a pplica t ions i n f or m a t ion gnd planes at these locations, due to their proximity to internal power handling components. the optimum number of thermal vias depends upon the printed circuit board design. for example, a board might use very small via holes. it should employ more thermal vias than a board that uses larger holes. the printed circuit board construction has an impact on the isolation performance of the end product. for example, increased trace and layer spacing, as well as the choice of core and prepreg materials ( such as using polyimide versus fr4) can significantly affect the isolation withstand of the end product. hot-plugging safely the small size, robustness and low impedance of ceramic capacitors make them an attractive option for the input bypass capacitor of the ltm8046. however, these capaci - tors can cause problems if the ltm8046 is plugged into a live supply ( see linear technology application note 88 for a complete discussion). the low loss ceramic capacitor combined with stray inductance in series with the power source forms an underdamped tank circuit, and the volt - age at the v in pin of the ltm8046 can ring to more than twice the nominal input voltage, possibly exceeding the ltm8046s rating and damaging the part. if the input supply is poorly controlled or the user will be plugging the ltm8046 into an energized supply, the input network should be designed to prevent this overshoot. this can be accomplished by installing a small resistor in series to v in , but the most popular method of controlling input voltage overshoot is adding an electrolytic bulk capacitor to v in . this capacitors relatively high equivalent series resistance damps the circuit and eliminates the voltage overshoot. the extra capacitor improves low frequency ripple filtering and can slightly improve the efficiency of the circuit, though it can be a large component in the circuit. thermal considerations the ltm8046 output current may need to be derated if it is required to operate in a high ambient temperature. the amount of current derating is dependent upon the input voltage, output power and ambient temperature. the temperature rise curves given in the typical performance characteristics section can be used as a guide. these curves were generated by the ltm8046 mounted to a 58cm 2 4-layer fr4 printed circuit board. boards of other sizes and layer count can exhibit different thermal behavior, so it is incumbent upon the user to verify proper operation over the intended systems line, load and environmental operating conditions. for increased accuracy and fidelity to the actual application, many designers use fea to predict thermal performance. to that end, the pin configuration section of the data sheet typically gives four thermal coefficients: ja : thermal resistance from junction to ambient jcbottom : thermal resistance from junction to the bot- tom of the product case jctop : thermal resistance from junction to top of the product case jb : thermal resistance from junction to the printed circuit board. while the meaning of each of these coefficients may seem to be intuitive, jedec has defined each to avoid confusion and inconsistency. these definitions are given in jesd 51-12, and are quoted or paraphrased as follows: ja is the natural convection junction- to- ambient air thermal resistance measured in a one cubic foot sealed enclosure. this environment is sometimes referred to as still air although natural convection causes the air to move. this value is determined with the part mounted to a jesd 51-9 defined test board, which does not reflect an actual application or viable operating condition. jcbottom is the junction-to-board thermal resistance with all of the component power dissipation flowing through the bottom of the package. in the typical module converter, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient envi - ronment. as a result, this thermal resistance value may be useful for comparing packages but the test conditions dont generally match the users application. ltm8046 8046fb
14 for more information www.linear.com/ltm8046 a pplica t ions i n f or m a t ion jctop is determined with nearly all of the component power dissipation flowing through the top of the package. as the electrical connections of the typical module converter are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junc - tion to the top of the part. as in the case of jcbottom , this value may be useful for comparing packages but the test conditions dont generally match the users application. jb is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the module converter and into the board, and is really the sum of the jcbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. the board temperature is measured a specified distance from the package, using a two-sided, two-layer board. this board is described in jesd 51-9. given these definitions, it should now be apparent that none of these thermal coefficients reflects an actual physical operating condition of a module converter. thus, none of them can be individually used to accurately predict the thermal performance of the product. likewise, it would be inappropriate to attempt to use any one coefficient to correlate to the junction temperature vs load graphs given in the products data sheet. the only appropriate way to use the coefficients is when running a detailed thermal analysis, such as fea, which considers all of the thermal resistances simultaneously. a graphical representation of these thermal resistances is given in figure 2. the blue resistances are contained within the module converter, and the green are outside. the die temperature of the ltm8046 must be lower than the maximum rating of 125 c, so care should be taken in the layout of the circuit to ensure good heat sinking of the ltm8046. the bulk of the heat flow out of the ltm8046 is through the bottom of the module and the bga pads into the printed circuit board. consequently a poor printed circuit board design can cause excessive heating, result - ing in impaired performance or reliability. please refer to the pcb layout section for printed circuit board design suggestions. figure 2. 8046 f02 module device junction-to-case (top) resistance junction-to-board resistance junction-to-ambient resistance (jesd 51-9 defined board) case (top)-to-ambient resistance board-to-ambient resistance junction-to-case (bottom) resistance junction ambient case (bottom)-to-board resistance ltm8046 8046fb
15 for more information www.linear.com/ltm8046 typical a pplica t ions 3.3v isolated flyback converter maximum output current vs v in v in (v) 0 maximum output current (ma) 800 700 500 600 300 400 200 10 20 8046 ta02b 30 2kvac isolation ltm8046 8046 ta02a v in 3.3v to 29v 3.3v v out 3.3v 11.8k 1f v out v in run fb ss bias gnd v out ? isolation barrier 100f 1f ltm8046 8046fb
16 for more information www.linear.com/ltm8046 typical a pplica t ions maximum output current vs v in use tw o ltm8046 flyback converters to generate 5v v in (v) 0 maximum output current (ma) 700 600 500 100 200 300 400 10 20 25 8046 ta03b 30 5 15 ltm8046 8046 ta03a ?5v 8.45k 1f v out v in run fb ss bias gnd v out ? 1f isolation barrier 2kvac isolation 1f 100f ltm8046 v in 4.3v to 26v 5v 8.45k 1f v out v in run fb ss bias gnd v out ? 1f isolation barrier 2kvac isolation 22f 100f 1f ltm8046 8046fb
17 for more information www.linear.com/ltm8046 pin name pin name pin name pin name pin name pin name pin name pin name pin name pin name pin name a1 v out b1 v out c1 v out C d1 - e1 - f1 - g1 gnd h 1 - j1 v in k1 v in l1 v in a2 v out b2 v out c2 v out C d2 - e2 - f2 - g2 gnd h 2 - j2 - k2 - l2 - a3 v out b3 v out c3 v out C d3 - e3 - f3 - g3 gnd h3 gnd j3 gnd k3 gnd l3 run a4 v out b4 v out c4 v out C d4 - e4 - f4 - g4 gnd h4 gnd j4 gnd k4 gnd l4 bias a5 v out C b5 v out C c5 v out C d5 - e5 - f5 - g5 gnd h5 gnd j5 gnd k5 gnd l5 ss a6 v out C b6 v out C c6 v out C d6 - e6 - f6 - g6 gnd h6 gnd j6 gnd k6 gnd l6 fb a7 v out C b7 v out C c7 v out C d7 - e7 - f7 - g7 gnd h7 gnd j7 gnd k7 gnd l7 gnd pin assignment table (arranged by pin number) p ackage descrip t ion p ackage p ho t o ltm8046 8046fb
18 for more information www.linear.com/ltm8046 p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. package top view 4 pin ?a1? corner y x aaa z aaa z detail a package bottom view 3 see notes l k j h g f e d c b a 1234567 pin 1 bga package 51-lead (15.00mm 9.00mm 4.92mm) (reference ltc dwg# 05-08-1889 rev ?) notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 5. primary datum -z- is seating plane 6. solder ball composition can be 96.5% sn/3.0% ag/0.5% cu or sn pb eutectic 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature detail a ?b (51 places) detail b substrate a a1 b1 ccc z detail b package side view mold cap z m x yzddd m zeee symbol a a1 a2 b b1 d e e f g h1 h2 aaa bbb ccc ddd eee min 4.72 0.50 4.22 0.71 0.60 0.27 3.95 nom 4.92 0.60 4.32 0.78 0.63 15.00 9.00 1.27 12.70 7.62 0.32 4.00 max 5.12 0.70 4.42 0.85 0.66 0.37 4.05 0.15 0.10 0.20 0.30 0.15 notes dimensions total number of balls: 51 a2 d e e b f g suggested pcb layout top view 0.000 3.810 5.080 3.810 6.350 5.080 6.350 2.540 1.270 3.810 2.540 1.270 3.810 2.540 1.270 0.3175 0.3175 0.000 // bbb z z h2 h1 0.630 0.025 ? 51x bga 51 1110 rev ? tray pin 1 bevel package in tray loading orientation component pin ?a1? ltmxxxxxx module ltm8046 8046fb
19 for more information www.linear.com/ltm8046 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 07/14 add mp-grade 2, 3 b 04/15 v in changed from 32v to 31v 1 ltm8046 8046fb
20 for more information www.linear.com/ltm8046 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 ? linear technology corporation 2014 lt 0415 rev b ? printed in usa (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltm8046 r ela t e d p ar t s typical a pplica t ion 12v isolated flyback converter maximum output current vs v in part number description comments ltm8057 ul60950 recognized 1.5w, 2kvac isolated module converter 3.1v v in 31v, 2.5v v out 12v, 5% v out accuracy, internal isolated transformer, 9mm 11.25mm 4.92mm bga ltm8058 ul60950 recognized 1.5w, 2kvac isolated module converter with ldo post regulator 3.1v v in 31v, 1.2v v out 12v, 2.5% v out accuracy, 1mv p-p output ripple, internal isolated transformer, 9mm 11.25mm 4.92mm bga ltm8048 1.5w, 725vdc galvanically isolated module converter with ldo post regulator 3.1v v in 32v, 1.2v v out 12v, 2.5% v out accuracy, 1mv p-p output ripple, internal isolated transformer, 9mm 11.25mm 4.92mm bga ltm8045 inverting or sepic module dc/dc converter with up to 700ma output current 2.8v v in 18v, 2.5v v out 15v, synchronizable, no derating or logic level shift for control inputs when inverting, 6.25mm 11.25mm 4.92mm bga ltm 4609 36v in , 5a dc/dc module buck-boost regulator 4.5v v in 36v, 0.8v v out 34v, adjustable soft-start, clock input, 15mm 15mm 2.82mm lga and 15mm 15mm 3.42mm bga ltm8061 32v, 2a step-down module battery charger with programmable input current limit suitable for charging single and dual cell li-ion or li-poly batteries, 4.95v v in 32v, c/10 or adjustable timer charge termination, ntc resistor monitor input, 9mm 15mm 4.32mm lga v in (v) maximum output current (ma) 8046 ta04b 12 6 9 3 300 250 150 200 50 100 0 2kvac isolation ltm8046 8046 ta04 v in 3.3vdc to 12vdc v out 12v 3.83k 1f 3.3v v out v in run fb ss bias gnd v out ? isolation barrier 10f 2 1f design r esources subject description module design and manufacturing resources design: ? selector guides ? demo boards and gerber files ? free simulation tools manufacturing: ? quick start guide ? pcb design, assembly and manufacturing guidelines ? package and board level reliability module regulator products search 1. sort table of products by parameters and download the result as a spread sheet. 2. search using the quick power search parametric table. techclip videos quick videos detailing how to bench test electrical and thermal performance of module products. digital power system management linear technologys family of digital power supply management ics are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature eeprom for storing user configurations and fault logging. ltm8046 8046fb

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